module sdata_convert(
			input	wire		sclk,
			input	wire		resetb,
			
			input	wire		vsin,
			input	wire		hsin,
			input	wire		dsin,
			input	wire	[7:0]	din,
			input	wire	[10:0]	h_num,
			input	wire		stop_sel,
			
			output	reg		vsout,
			output	reg		hsout,
			output	reg		dsout,
			output	reg	[31:0]	dout,
			output	reg		w_sel,
			output	wire		r_sel,
			output	reg	[10:0]	w_h_num
			);
			
reg	[2:0]	pixel_count;
reg	[7:0]	din_r,din_rr;

always@(posedge sclk)
begin
	hsout<=hsin;
	vsout<=vsin;
	w_h_num<=h_num;
end

always@(posedge sclk or negedge resetb)
	if(resetb==0)
		w_sel<=0;
	else if(vsout==0 && vsin==1 && stop_sel==0)
		w_sel<=~w_sel;

assign r_sel=~w_sel;

always@(posedge sclk or negedge resetb)
	if(resetb==0)
		pixel_count<=0;
	else if(hsin==0)
		pixel_count<=0;
	else if(dsin==1)
	begin
		if(pixel_count==2)
			pixel_count<=0;
		else
			pixel_count<=pixel_count+1;
	end

always@(posedge sclk)
begin
	din_r<=din;
	din_rr<=din_r;
end

always@(posedge sclk or negedge resetb)
	if(resetb==0)
		dout<=0;
	else if(pixel_count==2)
		dout<={8'b0,din[7:0],din_r[7:0],din_rr[7:0]};//31:24:N  23:16:B 15:8 G 7:0 R

always@(posedge sclk or negedge resetb)
	if(resetb==0)
		dsout<=0;
	else if(pixel_count==2)
		dsout<=1;
	else
		dsout<=0;

endmodule